Simulation and Verification of Self Test 16Bit Processor
نویسندگان
چکیده
منابع مشابه
Simulation and Verification of Self Test 16-Bit Processor
This paper presents the design and verification of 16 bit processor. The Booth multiplier and restoring division are integrated in to the ALU of the proposed processor. The processor is described in structural level to verify the general understanding of the system. The processor has 16-bit instruction based on three different format R-format, I-format and J-format. The control unit generates a...
متن کاملInstruction Randomization Self Test For Processor Cores
Access to embedded processor cores for application of test has greatly complicated the testability of large systems on silicon. Scan based testing methods cannot be applied to processor cores which cannot be modified to meet the design requirements for scan insertion. Instruction Randomization Self Test (IRST) achieves stuck-at-fault coverage for an embedded processor core without the need for ...
متن کاملGenerating concurrent test-programs with collisions for multi-processor verification
In this paper, we discuss collisions that are of interest to multiprocessor verification. Collisions occur when different processes access a shared resource. We investigate how the results of such collisions can be presented in test programs and suggest implementations for automatically generating such tests and predicting results of collision scenarios. Most of the ideas presented here are the...
متن کاملIndustrial Experience with Test Generation Languages for Processor Verification
We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the num...
متن کاملVerification of Processor Microarchitectures
This paper develops a new abstraction technique for processor microarchitecture validation. An abstract finite-state machine model is derived directly from the processor HDL description. This model, along with information about the instruction set is used for validation coverage analysis. We also present automatic test generation algorithms for generating sequences for traversing state transiti...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2011
ISSN: 0975-8887
DOI: 10.5120/2394-3180